Singer Sewing Machine Instruction Manuals Selected Athena product instruction manuals are available here for viewing in PDF format. To view or print pages from the manuals, you must have the Acrobat Reader plug-in installed. To obtain the free plug-in, click on the Acrobat Reader icon to the right and follow the instructions for installation. The Scalable Processor Architecture ( SPARC) is a (RISC) (ISA) originally developed.

Manual Probe Station. Vacuum chuck. Linear backlash free movement. Zero in on sub-micron target quickly and easily. Solomat Mpm 500E Manual. Solomat Mpm 5. Micro Precision Calibration Inc. SOLOMAT 8723 SOLOMAT MPM 500E SOLOMAT MPM1000 SOLOMAT MPM4000 SOLOMAT MPM500.

Since the establishment of SPARC International, Inc. In 1989, the SPARC architecture has been developed by its members. SPARC International is also responsible for licensing and promoting the SPARC architecture, managing SPARC trademarks (including SPARC, which it owns), and providing. SPARC International was intended to open the SPARC architecture to create a larger ecosystem; and SPARC has been licensed to several manufacturers, including,,, and. As a result of SPARC International, SPARC is fully open, non-proprietary and royalty-free. The first implementation of the original SPARC architecture (SPARC V7) were initially designed and used in Sun's and systems, replacing their earlier systems based on the of processors.

Later, SPARC processors were used in and servers produced by Sun, and, among others, and designed for operation. As of April 2017, the latest commercial high-end SPARC processors are 's (introduced in 2017 for its SPARC M12 server) and (introduced in 2015 for its PRIMEHPC FX100 supercomputer); and 's (introduced in October 2015 for its high-end servers). • ^ Threads per core × number of cores • Various SPARC V7 implementations were produced by Fujitsu,, Weitek, Texas Instruments and Cypress. A SPARC V7 processor generally consisted of several discrete chips, usually comprising an integer unit (IU), a (FPU), a (MMU) and cache memory. • @167 MHz • @250 MHz • @400 MHz • @440 MHz • max. @500 MHz • @900 MHz Operating system support [ ] SPARC machines have generally used Sun's,, or derived as, but other such as,,,,, and have also been used. In 1993, announced a port of to the SPARC architecture, but it was later cancelled.

In October 2015, Oracle announced a 'Linux for SPARC reference platform'. Open source implementations [ ] Several fully implementations of the SPARC architecture exist: •, a 32-bit, SPARC Version 8 implementation, designed especially for space use. Is written in, and licensed under the. •, released in 2006, a 64-bit, 32-thread implementation conforming to the UltraSPARC Architecture 2005 and to SPARC Version 9 (Level 1). Source code is written in, and licensed under many licenses. Most OpenSPARC T1 source code is licensed under the GPL. Source based on existent open source projects will continue to be licensed under their current licenses.

Binary programs are licensed under a binary. •, a 64-bit Wishbone compliant CPU core based on the OpenSPARC T1 design. It is a single UltraSPARC v9 core capable of 4-way SMT. Like the T1, the source code is licensed under the GPL. •, released in 2008, a 64-bit, 64-thread implementation conforming to the UltraSPARC Architecture 2007 and to SPARC Version 9 (Level 1).

Source code is written in Verilog, and licensed under many licenses. Most OpenSPARC T2 source code is licensed under the GPL. Source based on existing open source projects will continue to be licensed under their current licenses. Binary programs are licensed under a binary Software License Agreement. A fully simulator for the SPARC architecture also exists: •, a 32-bit, 64-thread SPARC Version 8 implementation, designed for FPGA-based architecture simulation.

RAMP Gold is written in ~36,000 lines of, and licensed under the. Supercomputers [ ] For HPC loads Fujitsu builds specialized processors with a new instruction extensions set called HPC-ACE (High Performance Computing – Arithmetic Computational Extensions). Fujitsu's ranked #1 in – June 2011 and November 2011 lists.

It combines 88,128 SPARC64 CPUs, each with eight cores, for a total of 705,024 cores – almost twice as many as any other system in the at that time. The K Computer was more powerful than the next five systems on the list combined, and had the highest performance-to-power ratio of any other supercomputer system. It also ranked #6 in – June 2011 list, with a score of 824.56 MFLOPS/W. In the November 2012 release of, the K computer ranked #3, using by far the most power of the top three. It ranked #85 on the corresponding release. Newer HPC processors, and, were included in recent and FX100 supercomputers.

( #1 as of November 2014 ) has a number of nodes with -based processors developed in China. However, those processors did not contribute to the score.

See also [ ] • – based on SPARC V7 specification • – a SPARC microprocessor developer during the 1980s and 1990s • – a modified SPARC with multiprocessing support used by the MIT Alewife project • – a space rated SPARC V8 processor. • – a Russian quad-core microprocessor based on SPARC V9 specification • – a Chinese 16-core OpenSPARC based processor References [ ]. Draft D1.0.0. January 12, 2016.

Retrieved June 13, 2016. #2-V8: An Oracle SPARC Architecture implementation may contain from 72 to 640 general-purpose 64-bit R registers. This corresponds to a grouping of the registers into MAXPGL + 1 sets of global R registers plus a circular stack of N_REG_WINDOWS sets of 16 registers each, known as register windows. The number of register windows present (N_REG_WINDOWS) is implementation dependent, within the range of 3 to 32 (inclusive).

•,,, retrieved January 8, 2013 •,, February 23, 2004, retrieved January 8, 2013 • Weaver, D. L.; Germond, T., eds. (1994), (PDF), SPARC International, Inc.,,, retrieved December 6, 2011 • 'SPARC Behavior and Implementation'.. Sun Microsystems, Inc. Retrieved September 24, 2011. There are four situations, however, when the hardware will not successfully complete a floating-point instruction. The instruction is not implemented by the hardware (such as.

Quad-precision instructions on any SPARC FPU). • (PDF),, May 21, 2014, retrieved November 25, 2015 • John Soat.. Oracle web site.. Retrieved October 13, 2015.

Partial list of numeric codes for verbs and nouns in the Apollo Guidance Computer. For a quick reference, they were printed on a side panel. Each lunar mission had two additional computers: The AGC was designed at the under, with hardware design led. Early came from,,,, and. The flight hardware was fabricated by, whose was also on the architectural team. The Apollo flight computer was the first computer to use. While the Block I version used 4,100 ICs, each containing a single three-input, the later Block II version (used in the crewed flights) used 2,800 ICs, each with dual three-input NOR gates.:34 The ICs, from, were implemented using (RTL) in a.

They were connected via, and the wiring was then embedded in cast plastic. The use of a single type of IC (the dual NOR3) throughout the AGC avoided problems that plagued another early IC computer design, the, which used a mix of and gates. The computer had 2048 words of erasable and 36 of.

Both had cycle times of 11.72 microseconds. The memory word length was 16 bits: 15 bits of data and one odd. The -internal word format was 14 bits of data, one bit, and one ( representation). DSKY interface [ ].

LM DSKY interface diagram. The to the AGC was the DSKY, standing for display and keyboard and usually pronounced dis-key. It had an array of indicator lights, numeric displays and a -style keyboard. Commands were entered numerically, as two-digit numbers:, and. Verb described the type of action to be performed and Noun specified which data was affected by the action specified by the Verb command. The numerals were displayed via green high-voltage. The segments were driven by electromechanical, which limited the display update rate.

Three five-digit signed numbers could also be displayed in or, and were typically used to display such as space craft or a required velocity change (). Although data was stored internally in, they were displayed as.

This calculator-style interface was the first of its kind, the prototype for all similar digital control panel interfaces. The Command Module had two DSKYs connected to its AGC: one located on the main instrument panel and a second located in the lower equipment bay near a used for aligning the platform. The Lunar Module had a single DSKY for its AGC. A (FDAI), controlled by the AGC, was located above the DSKY on the commander's console and on the LM.

In 2009, a DSKY was sold in a held by for,788. The AGC timing reference came from a 2.048 MHz.

The clock was divided by two to produce a which the AGC used to perform internal operations. The 1.024 MHz clock was also divided by two to produce a 512 kHz signal called the master frequency; this signal was used to synchronize external Apollo spacecraft systems. The master frequency was further divided through a, first by five using a ring counter to produce a 102.4 kHz signal. This was then divided by two through 17 successive stages called F1 (51.2 kHz) through F17 (0.78125 Hz). The F10 stage (100 Hz) was fed back into the AGC to increment the and other involuntary counters using Pinc (discussed below). The F17 stage was used to intermittently run the AGC when it was operating in the standby mode.

Central registers [ ] The AGC had four 16-bit for general computational use, called the central registers: A: The, for general computation Z: The – the address of the next instruction to be executed Q: The remainder from the DV instruction, and the after TC instructions LP: The lower product after MP instructions There were also four locations in core memory, at addresses 20-23, dubbed editing locations because whatever was stored there would emerge shifted or rotated by one bit position, except for one that shifted right seven bit positions, to extract one of the seven-bit interpretive op. Codes that were packed two to a word.

This was common to Block I and Block II AGCs. Other registers [ ].

Apollo AGC 1024-bit erasable module (front and back). Block I AGC memory was organized into 1 kiloword banks. The lowest bank (bank 0) was erasable memory (RAM).

All banks above bank 0 were fixed memory (ROM). Each AGC instruction had a 12-bit address field. The lower bits (1-10) addressed the memory inside each bank. Bits 11 and 12 selected the bank: 00 selected the erasable memory bank; 01 selected the lowest bank (bank 1) of fixed memory; 10 selected the next one (bank 2); and 11 selected the Bank register that could be used to select any bank above 2.

Banks 1 and 2 were called fixed-fixed memory, because they were always available, regardless of the contents of the Bank register. Banks 3 and above were called fixed-switchable because the selected bank was determined by the bank register. The Block I AGC initially had 12 kilowords of fixed memory, but this was later increased to 24 kilowords. Block II had 32 kilowords of fixed memory and 4 kilowords of erasable memory. The AGC transferred data to and from memory through the G register in a process called the memory cycle. The memory cycle took 12 timing pulses (11.72 μs).

The cycle began at timing pulse 1 (TP1) when the AGC loaded the memory address to be fetched into the S register. The memory hardware retrieved the data word from memory at the address specified by the S register. Words from erasable memory were deposited into the G register by timing pulse 6 (TP6); words from fixed memory were available by timing pulse 7. The retrieved memory word was then available in the G register for AGC access during timing pulses 7 through 10. After timing pulse 10, the data in the G register was written back to memory.

The AGC memory cycle occurred continuously during AGC operation. Instructions needing memory data had to access it during timing pulses 7-10. If the AGC changed the memory word in the G register, the changed word was written back to memory after timing pulse 10. In this way, data words cycled continuously from memory to the G register and then back again to memory.

The lower 15 bits of each memory word held AGC instructions or data, with each word being protected by a 16th odd parity bit. This bit was set to 1 or 0 by a parity generator circuit so a count of the 1s in each memory word would always produce an odd number. A parity checking circuit tested the parity bit during each memory cycle; if the bit didn't match the expected value, the memory word was assumed to be corrupted and a parity alarm panel light was illuminated.

Interrupts and involuntary counters [ ] The AGC had five vectored: • Dsrupt was triggered at regular intervals to update the user display (DSKY). • Erupt was generated by various hardware failures or alarms. • Keyrupt signaled a key press from the user's keyboard. • T3Rrupt was generated at regular intervals from a hardware timer to update the AGC's. • Uprupt was generated each time a 16-bit word of uplink data was loaded into the AGC. The AGC responded to each interrupt by temporarily suspending the current program, executing a short interrupt service routine, and then resuming the interrupted program. The AGC also had 20 involuntary.

These were memory locations which functioned as up/down counters, or shift registers. The counters would increment, decrement, or shift in response to internal inputs. The increment ( Pinc), decrement ( Minc), or shift ( Shinc) was handled by one subsequence of microinstructions inserted between any two regular instructions. Interrupts could be triggered when the counters overflowed. The T3rupt and Dsrupt interrupts were produced when their counters, driven by a 100 Hz hardware clock, overflowed after executing many Pinc subsequences.

The Uprupt interrupt was triggered after its counter, executing the Shinc subsequence, had shifted 16 bits of uplink data into the AGC. Standby mode [ ] The AGC had a power-saving mode controlled by a standby allowed switch.

This mode turned off the AGC power, except for the 2.048 MHz clock and the scaler. The F17 signal from the scaler turned the AGC power and the AGC back on at 1.28 second intervals.

In this mode, the AGC performed essential functions, checked the standby allowed switch, and, if still enabled, turned off the power and went back to sleep until the next F17 signal. In the standby mode, the AGC slept most of the time; therefore it was not awake to perform the Pinc instruction needed to update the AGC's real time clock at 10 ms intervals. To compensate, one of the functions performed by the AGC each time it awoke in the standby mode was to update the real time clock by 1.28 seconds. The standby mode was designed to reduce power by 5 to 10 W (from 70 W) during midcourse flight when the AGC was not needed.

However, in practice, the AGC was left on during all phases of the mission and this feature was never used. Data buses [ ] The AGC had a 16-bit read bus and a 16-bit write bus.

Data from central registers (A, Q, Z, or LP), or other internal registers could be gated onto the read bus with a control signal. The read bus connected to the write bus through a non-inverting buffer, so any data appearing on the read bus also appeared on the write bus.

Other control signals could copy write bus data back into the registers. Data transfers worked like this: To move the address of the next instruction from the B register to the S register, an RB (read B) control signal was issued; this caused the address to move from register B to the read bus, and then to the write bus. A WS (write S) control signal moved the address from the write bus into the S register.

Several registers could be read onto the read bus simultaneously. When this occurred, data from each register was inclusive- ORed onto the bus. This inclusive- OR feature was used to implement the Mask instruction, which was a logical AND operation.

Because the AGC had no native ability to do a logical AND, but could do a logical OR through the bus and could complement (invert) data through the C register, was used to implement the equivalent of a logical AND. This was accomplished by inverting both operands, performing a logical OR through the bus, and then inverting the result. Software [ ] AGC software was written in AGC and stored on. The bulk of the software was on read-only rope memory and thus couldn't be changed in operation, but some key parts of the software were stored in standard read-write and could be overwritten by the astronauts using the DSKY interface, as was done on. The design principles developed for the AGC by, directed in late 1960s by Charles Draper, became foundational to —particularly for the design of more reliable systems that relied on,, testing, and decision capability. When the design requirements for the AGC were defined, necessary software and programming techniques did not exist so it had to be designed from scratch. There was a simple designed by, consisting of the Exec, a batch job-scheduling using and an -driven called the Waitlist which could schedule multiple timer-driven 'tasks'.

The tasks were short threads of execution which could reschedule themselves for re-execution on the Waitlist, or could kick off a longer operation by starting a 'job' with the Exec. The AGC also had a sophisticated software interpreter, developed by the, that implemented a with more complex and capable pseudo-instructions than the native AGC. These instructions simplified the navigational programs. Interpreted code, which featured double precision, scalar and vector arithmetic (16 and 24-bit), even an MXV (matrix × vector) instruction, could be mixed with native AGC code. While the execution time of the pseudo-instructions was increased (due to the need to interpret these instructions at runtime) the interpreter provided many more instructions than AGC natively supported and the memory requirements were much lower than in the case of adding these instructions to the AGC native language which would require additional memory built into the computer (at that time the memory capacity was very expensive). The average pseudo-instruction required about 24 ms to execute. The assembler and system, named YUL for an early prototype Christmas Computer, enforced proper transitions between native and interpreted code.

A set of interrupt-driven user interface routines called Pinball provided keyboard and display services for the jobs and tasks running on the AGC. A rich set of user-accessible routines were provided to let the operator (astronaut) display the contents of various memory locations in or decimal in groups of 1, 2, or 3 registers at a time. Monitor routines were provided so the operator could initiate a task to periodically redisplay the contents of certain memory locations. Jobs could be initiated.

The Pinball routines performed the (very rough) equivalent of the UNIX shell. Many of the trajectory and guidance algorithms used were based on earlier work. The first command module flight was controlled by a software package called CORONA whose development was led by Alex Kosmala. Software for lunar missions consisted of COLOSSUS for the command module, whose development was led by Frederic Martin, and LUMINARY on the lunar module led by George Cherry. Details of these programs were implemented by a team under the direction of.

In total, software development on the project comprised 1400 of effort, with a peak workforce of 350 people. In 2016, Hamilton received the for her role in creating the flight software. Whirlpool Awm 285 800 User Manual. The Apollo Guidance Computer software influenced the design of Skylab, Space Shuttle and early fly-by-wire fighter aircraft systems. The AGC code was uploaded to the internet in 2003, and the software itself was uploaded by a former intern to on July 7, 2016. Block II [ ] A Block II version of the AGC was designed in 1966. It retained the basic Block I architecture, but increased erasable memory from 1 to 2 kilowords.

Fixed memory was expanded from 24 to 36 kilowords. Instructions were expanded from 11 to 34 and I/O channels were implemented to replace the I/O registers on Block I. The Block II version is the one that actually flew to the moon.

Block I was used during the unmanned and flights, and was on board the ill-fated. The decision to expand the memory and instruction set for Block II, but to retain the Block I's restrictive three-bit op. Code and 12-bit address had interesting design consequences. Various tricks were employed to squeeze in additional instructions, such as having special memory addresses which, when referenced, would implement a certain function.

For instance, an INDEX to address 25 triggered the RESUME instruction to return from an interrupt. Likewise, INDEX 17 performed an INHINT instruction (inhibit interrupts), while INDEX 16 reenabled them ( RELINT). Other instructions were implemented by preceding them with a special version of TC called EXTEND. The address spaces were extended by employing the Bank (fixed) and Ebank (erasable) registers, so the only memory of either type that could be addressed at any given time was the current bank, plus the small amount of fixed-fixed memory and the erasable memory. In addition, the bank register could address a maximum of 32 kilowords, so an Sbank (super-bank) register was required to access the last 4 kilowords.

All across-bank subroutine calls had to be initiated from fixed-fixed memory through special functions to restore the original bank during the return: essentially a system of. The Block II AGC also has the mysterious and poorly documented EDRUPT instruction (the name may be a contraction of Ed's Interrupt, after, the programmer who requested it) which is used a total of once in the Apollo software: in the Digital Autopilot of the. At this time, while the general operation of the instruction is understood, the precise details are still hazy, and it is believed to be responsible for problems emulating the LEM AGC. [ ] PGNCS trouble [ ] generated unanticipated warnings during, with the AGC showing a 1201 alarm ('Executive overflow - no vacant areas [ ]') and a 1202 alarm ('Executive overflow - no core sets'). The cause was a rapid, steady stream of spurious from the rendezvous radar, intentionally left on standby during the descent in case it was needed for an abort. During this part of the approach, the processor would normally be almost 85% loaded. The extra 6,400 cycle steals per second added the equivalent of 13% load, leaving just enough time for all scheduled tasks to run to completion.

Five minutes into the descent, Buzz Aldrin gave the computer the command 1668 which instructed it to calculate and display DELTAH (the difference between altitude sensed by the radar and the computed altitude). This added an additional 10% to the processor workload, causing executive overflow and a 1202 alarm. After being given the 'GO' from Houston, Aldrin entered 1668 again and another 1202 alarm occurred. When reporting the second alarm, Aldrin added the comment 'It appears to come up when we have a 1668 up'. Luckily for, the AGC software had been designed with priority scheduling.

Just as it had been designed to do, the software automatically recovered, deleting lower priority tasks including the 1668 display task, to complete its critical guidance and control tasks. Guidance controller and his support team that included issued several 'GO' calls and the landing was successful. For his role, Bales received the US on behalf of the entire control center team and the three Apollo astronauts. The problem was not a programming error in the AGC, nor was it pilot error. It was a peripheral hardware design bug that was already known and documented by Apollo 5 engineers. However, because the problem had only occurred once during testing, they concluded that it was safer to fly with the existing hardware that they had already tested, than to fly with a newer but largely untested radar system.

In the actual hardware, the position of the rendezvous radar was encoded with excited by a different source of 800 Hz AC than the one used by the computer as a timing reference. The two 800 Hz sources were frequency locked but not phase locked, and the small random phase variations made it appear as though the antenna was rapidly 'dithering' in position, even though it was completely stationary. These phantom movements generated the rapid series of cycle steals.

's software and computer design saved the Apollo 11 landing mission. Had it not been for Laning's design, the landing would have been aborted for lack of a stable guidance computer. Applications outside Apollo [ ]. Fly By Wire testbed aircraft. The AGC DSKY is visible in the avionics bay The AGC formed the basis of an experimental system installed into an to demonstrate the practicality of computer driven FBW. The AGC used in the first phase of the program was replaced with another machine in the second phase, and research done on the program led to the development of fly-by-wire systems for the.

The AGC also led, albeit indirectly, to the development of fly-by-wire systems for the generation of fighters that were being developed at the time. The AGC was also used for the 's. See also [ ].

As you know with most government agencies, when a new grant comes in, they have to justify the grant by buying new equipment leaving very useful equipment for surplus. Comes as shown! Powers up, includes 3 probes. Cosmetic wear. Guaranteed working, you have 14 days to try it out fully with right of return.

All international sales sold as is. It will probably work, but sold as is since we cannot test! We acquire 1000's of items each year from surplus and 99% work for our customers, but since we cant test it all items are sold as is. I chose used since it will most likely work, but didnt want to choose parts unit/non working since i dont know its exact condition.1.